Methods and circuits for protecting proprietary configuration data for programmable logic devices

No: 7373668
Antragsnr.: 10147600
Einreichungsdatum: 2002-05-17
Ausstellungsdatum: 2008-05-13
Art: B1
Anspruch: 15
Zeichnungsblatter: 14
Zusammenfassung: Described are methods and systems for encrypting and decrypting configuration data for programmable logic devices. An encrypted bitstream of configuration data includes two or more portions, each of which may be encrypted using a different key. Prior to loading, the author of each portion calculates the byte count for his or her portion and loads the required decryption key and byte count into a key and count memory. The designs are then loaded together as a single bitstream. The PLD decrypts the first portions using the first password. At the start of the partial bitstream, configuration logic loads the count associated with the decryption key for the first portions into a decrementing counter. The counter then decrements for each byte decrypted, reaching a count of zero when the first portion is fully decrypted. The configuration logic then selects the subsequent decryption key and associated count for the next portion of the bitstream.
US-Klassen:
	No:713 - Electrical computers and digital processing systems: support  / No:191 - Upgrade/install encryption
	No:713 - Electrical computers and digital processing systems: support  / No:193 - By stored data protection
Erfinder:
	Trimberger Stephen M.  (53)
Hauptuntersucher: Sheikh Ayaz
Hilfsuntersucher: Moorthy Aravind K
Agenten:
	Behiel Arthur J.  (82)
	Maunu LeRoy D.  (193)
Beauftragte:
	XILINX, Inc.} (ORG)  (37)
Suchbereich:
Auslandsurkunden:
	0253530 / 1987-05-31
	2424557 / 2006-08-31 / United Kingdom
	WO92/20157 / 1992-10-31
	WO94/10754 / 1993-10-31
	WO94/01867 / 1993-12-31
	WO9946774 / 1999-08-31
Andere Hinweise:
	Bossuet et al, Dynamically Configurable Security for SRAM FPGA Bitstreams, 2004, French Ministry for Education and Research, pp. 1-12.
	Kean, Tom, Secure Configuration of Field Programmable Gate Arrays, Algotronix Consulting, pp. 1-10.
	Xilinx Application Note, “Configuration Issues: Power-Up, Volatility, Security, Battery Back-Up”, By Peter Alfke, XAPP 092, Nov. 24, 1997 (Version 1.1).
	Virtex Configuration Guide, published by Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, Oct. 9, 2000 (Version 1.0).
	Bruce Schneier “Applied Cryptography: Protocols, Algorithms, and Source Code in C”, Second Edition, Copyright 1996, published by John Wiley & Sons, Inc.; Chapter 9, pp. 193-194, Chapter 10, 200-203 and p. 216; Chapter 12, pp. 265-301, Chapter 15, pp. 360-361, p. 456 and 483-502.
	Cahners EDN ACCESS Web Page, “Cunning circuits confound crooks,” Oct. 12, 2000; pp. 1-8; http://www.ednmag.com/ednmag/reg/2000/10122000/21df2.htm.
	Xilinx, Application Note, XAPP138, “Virtex FPGA Series Configuration and Readback”, published Oct. 4, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
	Wolfgang Hoflich, Applications Note, “Using the XC4000 Readback Capability”, XAPP 015.000, 1993, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, pp. 8-37 to 8-44.
	Ann Duncan, Application Note, “DES Encryption and Decryption on the XC6216”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, XAPP 106, Feb. 2, 1998 (version 1.0), pp. 1-7.
	“XC9500 In-System Programmable CPLD Family”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, Sep. 15, 1999 (version 5.0), pp. 1-16.
	Product Specification, “XC18V00 Series of In-System Programmable Configuration PROMs”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, Nov. 12, 2001, DS026, (version 3.0), pp. 1-19.
	Advanced Product Specification, “XC9500XV Family High-Performance CPLD”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, Jan. 15, 2001, DS049, (version 2.0), pp. 1-18.
	“The Programmable Logic Data Book”, published 1998, pp. 4-46 through 4-59, available from Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
	“The Programmable Logic Data Book”, published 1994, pp. 2-105, through 2-132, 2-231 through 2-235, available from Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
	Menezes, A. J., et al., Handbook of Applied Cryptography, 1996, CRC Press, pp. 338-363.
	Johnson, Mark G.; “Encryption Code (three different sources)” Jan. 18, 1991. usenet:sci.crypt. Relevant code on p. 20 of printout.
	Cristiano, Paris; “Burn! Burn it all!” Oct. 7, 1996. usenet: sci.crypt.
	Dipert, Brian; “Cunning Circuits Confound Crooks,” Oct. 12, 2000. Cahners EDN Access.
	Hamalainen et al.; “Configurable Hardware Implementation of Triple-DES Encryption Algorithm For Wireless Local Area Network”, May 2001; IEEE Proceedings, (ICASSP '01) vol. 2, May 7-11, 2001, pp. 1221-1224, vol. 2.
	Schneier, Bruce; “Applied Cyptography” 1996. John Wiley & Sons pp. 283-284, 360.
	National Institute of Standards and Technology “Announcing Draft Federal Information Processing Standard (FIPS) 46-3, Data Encryption Standar (DES), and Request for Comments”, Jan. 15, 1999.
	Rubin, Paul et al., “What Do You Do With Boken Crypto Hardware?” Jan. 25, 2001, pp. 1-4. usenet:sci.crypt.
	Menezes, A. J., et al., Handbook of Applied Cryptography, 1996, CRC Press, pp. 578-581.
	U.S. Appl. No. 10/147,664 filed May 17, 2002, Trimberger, Stephen M., entitled “Methods and Systems for Encrypting Proprietary Configuration Data for Programmable Logic Devices”, Xilinx, Inc., San Jose, CA 95124 (66 pgs).
	U.S. Appl. No. 10/150,272 filed May 17, 2002, Trimberger, Stephen M., entitled “Self-Erasing memory for Protecting Decryption Keys and Proprietary Configuration”, Xilinx, Inc., San Jose, CA 95124, (66 pgs).
	U.S. Appl. No. 10/150,289 filed May 17, 2002, Trimberger, Stephen M., entitled “Methods and Circuits for Maintaining Decryption-Key Security for Use in Programmable Logic Devices”, Xilinx, Inc., San Jose, CA 95124 (65 pgs.).
	U.S. Appl. No. 10/150,308 filed May 17, 2002, Trimberger, Stephen M., entitled “Programmable Logic Device that Supports Secure and Non-Secure Modes of Decryption-Key Access”, Xilinx, Inc., San Jose, CA 95124 (65 pgs.).
Hinweise:
	3849760
	4037214
	4757468
	5084636
	5091938
	5121359
	5237218
	5237219
	5237611
	5293424
	5321704
	5327564
	5336950
	5341034
	5343406
	5349249
	5375169
	5388157
	5394031
	5442704
	5457408
	5581510
	5594793
	5598424
	5748740
	5768372
	5774544
	5838901
	5890199
	5914616
	5930826
	5933023
	5974500
	5978476
	5982899
	6028445
	6049222
	6058477
	6118869
	6172520
	6212639
	6237124
	6255849
	6259791
	6305005
	6324676
	6330668
	6331784
	6336176
	6356637
	6357037
	6366117
	6367011
	6438065
	6441641
	6442092
	6457125
	6473861
	6477677
	6598161
	6615329
	6636971
	6662333
	6738962
	6785816
	6823069
	Microcontroller having embedded non-volatile memory with read protection
	Intellectual property protection in a programmable logic device
	Methods and systems for generating encryption keys using random bit generators
	Programmable logic device with decryption algorithm and decryption key
	Erase block management
	Encryption key for multi-key encryption in programmable logic device
	Method and apparatus for streaming data using rotating cryptographic keys
	Methods and circuits for preventing the overwriting of memory frames in programmable logic devices
	Methods and circuits for protecting proprietary configuration data for programmable logic devices
	Error-checking and correcting decryption-key memory for programmable logic devices
	Read- and write-access control circuits for decryption-key memories on programmable logic devices